The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. These circuits may be sensitive to electrostatic discharge (ESD) currents. Thus, ESD protection devices are utilized to prevent and reduce damages to an IC caused by ESD currents. Traditionally, an ESD protection device utilizes a silicide-blocking layer to prevent a silicide from forming on a drain region of the ESD device, thereby suppressing an ESD discharging current and preventing non-uniform turn-on issues in the ESD protection device. However, implementing the silicide-blocking layer increases fabrication costs and may require a larger chip area.
Therefore, while existing methods of fabricating ESD protection devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.